Semiconductor and micromechanical dies or chips are frequently packaged for protection against an external environment. The package provides physical protection, stability, external connections, and in some cases, cooling to the die inside the packages. Typically the die is attached to a substrate and then a cover that attaches to the substrate is placed over the die. Alternatively, the die is attached to a cover and then a package substrate or redistribution layer is formed on the die. In some cases a die cover extends laterally past the die area and the redistribution layer is applied to the die area and the lateral extension to form a fan-out package.
Wafer Level Ball Grid Array (WLB) packages and other packages often use a dielectric layer between the chip surface and the redistribution layers. The dielectric layer mechanically protects the die surface and functions as a stress buffer. This helps to ensure that stresses from a printed circuit board do not damage the package or the package connections to the board. The dielectric layer also defines a gap or distance between the functional metal structures of the die and the redistribution layers that connect to the board. This gap improves electrical performance, by limiting capacitive coupling between the RDL and the die surface. In addition, a defined gap between the RDL and the chip surface allows transmission lines to be built between the two with a well-defined line impedance. Other types of packages use a dielectric layer between the chip surface and package substrate.